1. Field of the Invention
The present invention relates to a semiconductor device and method of fabricating the same, and more particularly, to a complementary metal oxide semiconductor (CMOS) device having improved performance and a method of fabricating the same.
2. Description of the Related Art
A CMOS device comprises both N-type MOS (NMOS) and P-type MOS (PMOS) transistors. The major carriers are electrons in the NMOS transistor while the major carriers are holes in the PMOS transistor. Thus, in order to improve the overall performance of the CMOS device, a balance between performance of NMOS and PMOS transistors within the CMOS device must be achieved.
It is generally known that electron mobility in a semiconductor substrate is about 2 to 2.5 times higher than hole mobility in the semiconductor substrate. Thus, a conventional CMOS device is designed such that a channel width of a PMOS transistor is about 2 to 2.5 times greater than that of an NMOS transistor.
Nevertheless, since electrons and holes respond to external stresses in opposite directions, an imbalance in performance between PMOS and NMOS transistors is unavoidably generated.
Therefore, development of a CMOS device having improved performance while still employing a conventional stable CMOS fabrication process without requiring a separate process of eliminating the imbalance in transistor performance would be highly desirable.